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Modified files:
books/developers-handbook/dma chapter.sgml
books/developers-handbook/x86 chapter.sgml
Log:
Ubersetzungen:
- Kapitel 9
- Kapitel 12.14
- Kapitel 12.15
uebersetzt von ds@
Revision Changes Path
1.2 +500 -481 de-docproj/books/developers-handbook/dma/chapter.sgml
1.2 +114 -168 de-docproj/books/developers-handbook/x86/chapter.sgml
Index: chapter.sgml
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Reserved. 10 December 1996. Last Update 8 October
1997.</emphasis></para>
- <para>Direct Memory Access (DMA) is a method of allowing data to be moved
- from one location to another in a computer without intervention from the
- central processor (CPU).</para>
-
- <para>The way that the DMA function is implemented varies between computer
- architectures, so this discussion will limit itself to the
- implementation and workings of the DMA subsystem on the IBM Personal
- Computer (PC), the IBM PC/AT and all of its successors and
- clones.</para>
-
- <para>The PC DMA subsystem is based on the &intel; 8237 DMA controller. The
- 8237 contains four DMA channels that can be programmed independently and
- any one of the channels may be active at any moment. These channels are
- numbered 0, 1, 2 and 3. Starting with the PC/AT, IBM added a second
- 8237 chip, and numbered those channels 4, 5, 6 and 7.</para>
-
- <para>The original DMA controller (0, 1, 2 and 3) moves one byte in each
- transfer. The second DMA controller (4, 5, 6, and 7) moves 16-bits from
- two adjacent memory locations in each transfer, with the first byte
- always coming from an even-numbered address. The two controllers are
- identical components and the difference in transfer size is caused by
- the way the second controller is wired into the system.</para>
-
- <para>The 8237 has two electrical signals for each channel, named DRQ and
- -DACK. There are additional signals with the names HRQ (Hold Request),
- HLDA (Hold Acknowledge), -EOP (End of Process), and the bus control
- signals -MEMR (Memory Read), -MEMW (Memory Write), -IOR (I/O Read), and
- -IOW (I/O Write).</para>
-
- <para>The 8237 DMA is known as a <quote>fly-by</quote> DMA controller.
- This means that the data being moved from one location to another does
- not pass through the DMA chip and is not stored in the DMA chip.
- Subsequently, the DMA can only transfer data between an I/O port and a
- memory address, but not between two I/O ports or two memory
- locations.</para>
+ <para>Direct Memory Access (DMA) ist eine Methode, die es erlaubt, Daten von
+ einer stelle in einem Rechnern an eine andere zu transferieren ohne
+ Eingreifen des Prozessors (CPU).</para>
+
+ <para>Die Art und Weise, in der die DMA-Funktion implementiert ist, variiert
+ zwischen den Rechnerarchitekturen. Daher beschränken wir uns im Folgenden
+ ausschliesslich auf die Methoden und Implementierungen auf IBM
+ Personal Computer (PC), dem IBM PC/AT und all seinen Nachfolgern und
+ Nachbauten.</para>
+
+ <para>Das DMA-Subsystem basiert auf dem &intel; 8237 DMA-Controller. Der
+ 8237 enthält vier DMA-Kanäle, welche unabhängig voneinander programmiert
+ werden können und jeder dieser Kanäle kann zu einem beliebigen Zeitpunkt
+ aktiv sein. Diese Kanäle sind mit 0, 1, 2 und 3 nummeriert. Beginnend
+ mit dem PC/AT fügte IBM einen zweiten 8237-Chip hinzu und nummerierte
+ dessen Kanäle mit 4, 5, 6 und 7.</para>
+
+ <para>Der originale DMA-Controller (0, 1, 2 and 3) bewegt ein Byte bei jedem
+ Transfer. Der zweite DMA-Controller (4, 5, 6, and 7) bewegt 16-Bits aus
+ zwei benachbarten Speicherbereichen bei jedem Transfer, wobei das erste Byte
+ immer von einer geradzahligen Adresse stammt. Die zwei Controller sind
+ identische Komponenten und der Unterschied in der Transfergröße wird durch
+ die Art und Weise verursacht, wie der zweite Controller im System
+ beschaltet ist.</para>
+
+ <para>Der 8237 hat zwei elektrische Signale für jeden Kanal: DRQ und
+ -DACK. Zusätzlich gibt es weitere Signale mit den Namen HRQ (Hold Request),
+ HLDA (Hold Acknowledge), -EOP (End of Process) sowie die Kontrollsignale
+ für den Bus: -MEMR (Memory Read), -MEMW (Memory Write), -IOR (I/O Read)
+ und -IOW (I/O Write).</para>
+
+ <para>Der 8237 DMA-Controller ist bekannt als ein <quote>fly-by</quote>-DMA-Controller.
+ Das bedeutet, daß die von einem zu einem anderen Bereich bewegten Daten
+ weder den DMA-Chip durchlaufen noch darin gespeichert werden. Daraus
+ folgernd kann der DMA-Controller nur zwischen einem I/O-Port und einer Speicheradresse
+ Daten bewegen, nicht zwischen zwei I/O-Ports oder zwei Speicherbereichen.</para>
<note>
- <para>The 8237 does allow two channels to be connected together to allow
- memory-to-memory DMA operations in a non-<quote>fly-by</quote> mode,
- but nobody in the PC industry uses this scarce resource this way since
- it is faster to move data between memory locations using the
- CPU.</para>
+ <para>Der 8237 erlaubt es, daß zwei Kanäle verbunden sind, um einen
+ höheren Durchsatz bei DMA-Operationen zwischen verschiedenen Speicherbereichen
+ in einem nicht-<quote>fly-by</quote>-Modus zu gewährleisten. Aber niemand
+ in der PC-Industrie benutzt diese begrenzte Resource, da es schneller ist
+ die Daten mittels der CPU zwischen Speicherbereichen zu bewegen.</para>
</note>
- <para>In the PC architecture, each DMA channel is normally activated only
- when the hardware that uses a given DMA channel requests a transfer by
- asserting the DRQ line for that channel.</para>
+ <para>In der PC-Architekur wird jeder DMA-Kanal normalerweise nur dann
+ aktiviert, wenn die Hardware, welche einen gegebenen DMA-Kanal benutzt,
+ einen Transfer durch Setzen der DRQ-Linie verlangt.</para>
<sect2>
- <title>A Sample DMA transfer</title>
+ <title>Beispiel eines DMA-Transfers</title>
- <para>Here is an example of the steps that occur to cause and perform a
- DMA transfer. In this example, the floppy disk controller (FDC) has
- just read a byte from a diskette and wants the DMA to place it in
- memory at location 0x00123456. The process begins by the FDC
- asserting the DRQ2 signal (the DRQ line for DMA channel 2) to alert
- the DMA controller.</para>
-
- <para>The DMA controller will note that the DRQ2 signal is asserted. The
- DMA controller will then make sure that DMA channel 2 has been
- programmed and is unmasked (enabled). The DMA controller also makes
- sure that none of the other DMA channels are active or want to be
- active and have a higher priority. Once these checks are complete,
- the DMA asks the CPU to release the bus so that the DMA may use the
- bus. The DMA requests the bus by asserting the HRQ signal which goes
- to the CPU.</para>
-
- <para>The CPU detects the HRQ signal, and will complete executing the
- current instruction. Once the processor has reached a state where it
- can release the bus, it will. Now all of the signals normally
- generated by the CPU (-MEMR, -MEMW, -IOR, -IOW and a few others) are
- placed in a tri-stated condition (neither high or low) and then the
- CPU asserts the HLDA signal which tells the DMA controller that it is
- now in charge of the bus.</para>
-
- <para>Depending on the processor, the CPU may be able to execute a few
- additional instructions now that it no longer has the bus, but the CPU
- will eventually have to wait when it reaches an instruction that must
- read something from memory that is not in the internal processor cache
- or pipeline.</para>
-
- <para>Now that the DMA <quote>is in charge</quote>, the DMA activates its
- -MEMR, -MEMW, -IOR, -IOW output signals, and the address outputs from
- the DMA are set to 0x3456, which will be used to direct the byte that
- is about to transferred to a specific memory location.</para>
-
- <para>The DMA will then let the device that requested the DMA transfer
- know that the transfer is commencing. This is done by asserting the
- -DACK signal, or in the case of the floppy disk controller, -DACK2 is
- asserted.</para>
-
- <para>The floppy disk controller is now responsible for placing the byte
- to be transferred on the bus Data lines. Unless the floppy controller
- needs more time to get the data byte on the bus (and if the peripheral
- does need more time it alerts the DMA via the READY signal), the DMA
- will wait one DMA clock, and then de-assert the -MEMW and -IOR signals
- so that the memory will latch and store the byte that was on the bus,
- and the FDC will know that the byte has been transferred.</para>
-
- <para>Since the DMA cycle only transfers a single byte at a time, the
- FDC now drops the DRQ2 signal, so the DMA knows that it is no longer
- needed. The DMA will de-assert the -DACK2 signal, so that the FDC
- knows it must stop placing data on the bus.</para>
-
- <para>The DMA will now check to see if any of the other DMA channels
- have any work to do. If none of the channels have their DRQ lines
- asserted, the DMA controller has completed its work and will now
- tri-state the -MEMR, -MEMW, -IOR, -IOW and address signals.</para>
-
- <para>Finally, the DMA will de-assert the HRQ signal. The CPU sees
- this, and de-asserts the HOLDA signal. Now the CPU activates its
- -MEMR, -MEMW, -IOR, -IOW and address lines, and it resumes executing
- instructions and accessing main memory and the peripherals.</para>
-
- <para>For a typical floppy disk sector, the above process is repeated
- 512 times, once for each byte. Each time a byte is transferred, the
- address register in the DMA is incremented and the counter in the DMA
- that shows how many bytes are to be transferred is decremented.</para>
-
- <para>When the counter reaches zero, the DMA asserts the EOP signal,
- which indicates that the counter has reached zero and no more data
- will be transferred until the DMA controller is reprogrammed by the
- CPU. This event is also called the Terminal Count (TC). There is only
- one EOP signal, and since only one DMA channel can be active at any
- instant, the DMA channel that is currently active must be the DMA
- channel that just completed its task.</para>
-
- <para>If a peripheral wants to generate an interrupt when the transfer
- of a buffer is complete, it can test for its -DACKn signal and the EOP
- signal both being asserted at the same time. When that happens, it
- means the DMA will not transfer any more information for that
- peripheral without intervention by the CPU. The peripheral can then
- assert one of the interrupt signals to get the processors' attention.
- In the PC architecture, the DMA chip itself is not capable of
- generating an interrupt. The peripheral and its associated hardware
- is responsible for generating any interrupt that occurs.
- Subsequently, it is possible to have a peripheral that uses DMA but
- does not use interrupts.</para>
-
- <para>It is important to understand that although the CPU always
- releases the bus to the DMA when the DMA makes the request, this
- action is invisible to both applications and the operating system,
- except for slight changes in the amount of time the processor takes to
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Received on Tue 07 Aug 2007 - 17:00:27 CEST